1. Field of the Invention
The invention relates to driver circuits and to integrated circuits including such driver circuits.
2. Description of the Prior Art
A typical driver circuit comprises one or more devices which are driven (alternately) into saturation. The accompanying FIG. 1 illustrates a typical CMOS output driver stage of a driver circuit 10 comprising a first output driver 12, here a PMOS transistor 12, and a second output driver, here an NMOS transistor 14 in series between a high voltage supply Vdd 16 and a low voltage supply Vss 18. The PMOS and NMOS transistors 12 and 14 are alternatively driven into saturation by a signal A supplied at an input 20. The driven signal Y is output at 22 to I/O devices 24.
The operation of the driver stage of FIG. 1 will now be described. Consider the situation where signal A is low. The gate of the PMOS device 12 will be low, which turns the PMOS device 12 on and provides a low impedance path from the output at 22 to the high voltage line Vdd 16. At this time, the NMOS device 14 is turned off. Accordingly, the signal at the output 22 goes high providing a high driven signal. When the signal A is high, the gate of the NMOS device 14 is turned on, providing a low impedance path from the output 22 to the low voltage line Vss 18. At this time, the PMOS device 12 is turned off. Accordingly, the signal at the output 22 goes low providing a low signal Y.
A problem arises when the supply at Vdd or at Vss varies. Unwanted variations can result from DC drift, Vdd or Vss supply or ground"bounce", or other effects. This can occur, for example, due to electromagnetic interference, or to noise spikes caused in the circuitry of an integrated circuit of which the driver stage forms a part. Accordingly, rather than there being a fixed voltage level at Vdd and another fixed voltage level at Vss, the voltages at either or both of these supply lines 16 and 18 can vary significantly, and independently of one another. Accordingly, since the output 22 is always connected via a low impedance path directly to either Vdd or Vss, any supply variations will be translated directed into unwanted variations on the output level of the signal Y. Typically, in straight CMOS-CMOS applications, a receiver stage which is downstream of the driver stage is tolerant of this noise until it exceeds half the supply rail voltage, at which time the receiver will erroneously receive the wrong voltage level and will switch accordingly.
FIG. 2 illustrates another type of prior art output driver circuit 30 which employs a "bridge" circuit, as is typically associated with high power electric motor drives. It has been proposed to use the circuit of FIG. 2 as a high speed driver circuit.
In FIG. 2, the bridge arrangement 32 comprises a first output driver 34 formed by a pair of PMOS output drive devices 38 and 40 and a second output driver 36 formed by a pair of NMOS output drive devices 42 and 44. A first PMOS device 38 is connected between the supply line 16 and a first output line 60. A second PMOS device 40 is connected between the high voltage supply line 16 and a second output line 62. A first NMOS device 42 is connected between the low voltage supply line 18 and the first output line 60. A second NMOS device 44 is connected between the low voltage supply line 18 and the second output line 62. Signals A and A are provided for controlling the PMOS and NMOS devices 38, 40, 42 and 44. Specifically, a phase splitter 50 is provided for splitting a CMOS input into a first signal A 46 and a complementary signal A 48.
In a first phase, the signal A to the PMOS device 40 and the NMOS device 44 is high and the signal A to the PMOS device 38 and the NMOS device 42 is low. These signals causes low impedance paths from the high voltage supply Vdd to the first output line 60 via PMOS device 38 and from the low voltage supply Vss to the second output line 62 via NMOS transistor 44 to be established.
In a second phase, the signal A to the PMOS device 40 and the NMOS device 44 is low and the signal A to the PMOS device 38 and the NMOS device 42 is high. These signals causes low impedance paths from the high voltage supply Vdd to the second output line 62 via PMOS device 40 and from the low voltage supply Vss to the first output line 60 via NMOS transistor 42 to be established.
Accordingly, as a result of the application of the complementary signals A and A to the output drive devices of the bridge 32, an output signal Y is supplied on the first output line 60 by alternatively connecting the output line 60 to the high voltage supply line Vdd 16 and to the low voltage supply line Vss 18 and a complementary driven output Y is provided on line 62 by alternately connecting the output line 62 to the low voltage supply line Vss 18 and to the high voltage supply line Vdd 16 out of phase with the connection of the output line 60.
The output lines 60 and 62 are connected via a nominal resistance of 100 .OMEGA. formed by two separate resistors, each having a nominal resistance of 50 .OMEGA.. A central tap 54 between the 50 .OMEGA. resistors 56 and 58 is supplied to an error amplifier 52 which compares the error amplifier to a common mode reference voltage 64 supplied from an EUSCIBIAS circuit 68. This establishes a nominal common mode reference using a reference bias resistance 70. The EUSCIBIAS circuit 68 also provides output current control signals 66 to the error amplifier 52. The error amplifier 52 is responsive to changes in the common mode voltage detected at the point 54 with respect to the common mode reference 64 to adjust bias currents provided by current sources 76 and 78. The DC characteristics of this off-chip output driver circuit is determined in response to the error amplifier 52 which corrects the output common mode voltage by varying the two bias currents in opposite directions and varies the two bias currents in the same direction to track the external bias resistor connected to the EUSCIBIAS circuit 68. The common mode bias point is measured, as indicated above, by monitoring the centre-tap 54 of the output resistances 56 and 58.
The provision of the bias current sources 76 and 78 results in a reduction of the available voltage differential of the differential output signals. For example, where the Vss rail is at 0 V and the Vdd rail is at 3 V, the reduction in the potential difference is to about 1.8 V.
Although the circuit described with respect to FIG. 2 does provide for correcting the common mode voltage and to track the external resistor 70, it also suffers from the problem that unwanted variations in the supply or ground levels will be translated directly into unwanted level shifts in the differential output signals Y and Y.
It can thus be seen that the conventional driver stages suffer from significant disadvantages. In the CMOS design of FIG. 1, the output ports are connected directly via one saturated device to the power supply or ground so that the output stage high and low levels are sensitive to unwanted supply variation. Furthermore, circuit component manufacturing process tolerance variations also affect the output drive signal levels.
In the design of FIG. 2, although the problem of having saturated devices connecting the driven outputs to the supplies is eliminated, the control device levels are still left open and are subject to circuit component variations.
Accordingly, an aim of the invention is substantially to eliminate or at least to mitigate the problems of prior art driver circuits.